NXP Semiconductors /MIMXRT1011 /IOMUXC /SW_MUX_CTL_PAD_GPIO_AD_09

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SW_MUX_CTL_PAD_GPIO_AD_09

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ALT0)MUX_MODE 0 (DISABLED)SION

SION=DISABLED, MUX_MODE=ALT0

Description

SW_MUX_CTL_PAD_GPIO_AD_09 SW MUX Control Register

Fields

MUX_MODE

MUX Mode Select Field.

0 (ALT0): Select mux mode: ALT0 mux port: LPSPI2_SDI of instance: LPSPI2

1 (ALT1): Select mux mode: ALT1 mux port: FLEXPWM1_PWM3_X of instance: FLEXPWM1

2 (ALT2): Select mux mode: ALT2 mux port: KPP_ROW02 of instance: KPP

3 (ALT3): Select mux mode: ALT3 mux port: ARM_TRACE_SWO of instance: cm7_mxrt

4 (ALT4): Select mux mode: ALT4 mux port: FLEXIO1_IO21 of instance: FLEXIO1

5 (ALT5): Select mux mode: ALT5 mux port: GPIOMUX_IO23 of instance: GPIOMUX

6 (ALT6): Select mux mode: ALT6 mux port: REF_32K_OUT of instance: anatop

7 (ALT7): Select mux mode: ALT7 mux port: JTAG_TDO of instance: JTAG

SION

Software Input On Field.

0 (DISABLED): Input Path is determined by functionality

1 (ENABLED): Force input path of pad GPIO_AD_09

Links

() ()